Technology Mapping for Heterogeneous FPGAs

Truly heterogenous FPGAs, those with two diierent kinds of logic block, don't exist in the commercial world in part because logic synthesis for them is diicult. The diiculty arises because FPGAs are prefabricated , and so the ratio of the number of each type of block is xed, which requires a constraint on the mapping that is not present for either homogenous FPGAs or ASICs. This paper presents a general approach for technology mapping into heterogenous lookup-table based FPGAs. It is applied both at the boolean network node level and at a more global level across a collection of mapped sub-circuits. This latter portion of the algorithm is optimal, and is applicable to any heterogenous FPGA, not simply those based on lookup tables. In comparison to a reasonably obvious alternative approach (adjusting the output of an homogenous mapping algorithm) the new algorithm achieves, depending on the heterogenous architecture, an average improvement of up to 48% over a large set of benchmark circuits.